Adaptec AIC-6915 Informazioni Techniche Pagina 113
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7-41
Register Descriptions
TxDescQueueConsumerIndex Register
Type: R/W
Internal Registers Su/jointfilesconvert/419897/bgroup: Ethernet Functional Registers
Byte Address: A4h- A7h
TxDmaStatus1
Type: R
Internal Registers Su/jointfilesconvert/419897/bgroup: Ethernet Functional Registers
Byte Address: A8h - ABh
Table 7-51. TxDescQueueConsumerIndex Register
Bit(s) rw
Reset
Value Description/Function
31:27 r 0
Reserved:
Always read as ‘0’.
26:16 r 0
HiPrTxConsumerIndex:
Written by the AIC-6915 and read by the
software driver. This field points to an 8-byte entry in the
low-priority DMA descriptor queue. The AIC-6915 increments
H
I
P
R
T
X
C
ONSUMER
I
NDEX
after it completes the fetching of the
descriptors from host memory. The software driver can write this
field only if
T
X
D
MA
E
N
is reset to ‘0’. In this case, the queue is
disabled and the AIC-6915 cannot continue on to fetch the next
descriptor
.
The producer and consumer indices point to a
doubleword (8-byte) address in the queue.
15:11 r 0
Reserved:
Always reads 0.
10:0 r 0
LoPrTxConsumerIndex:
Written by the AIC-6915 and read by the
software driver. This field points to an 8-byte entry in the
low-priority DMA descriptor queue. The AIC-6915 increments
L
O
P
R
T
X
C
ONSUMER
I
NDEX
after it completes fetching the descriptors
from host memory. The software driver can write this field only if
T
X
D
MA
E
N
is reset to ‘0’. In this case the queue is disabled and the
AIC-6915 cannot continue on to fetch the next descriptor. The
producer and consumer indices point to a doubleword (8-byte
address) in the queue.
Table 7-52. TxDmaStatus1 Register
Bit(s) rw
Reset
Value Description/Function
31:24 r 0
TxFifoEngineState:
Indicates the state of the internal transmit DMA
FP FIFO engine state machine.
23:11 r 0
EndOfFrameBufferPtr:
This is the current end of frame FIFO
Pointer.
10:2 r 0
TxDmaState:
Indicates the state of the internal transmit DMA state
machine.
1r0
Reserved
.
0r0
Reserved.
- AIC-6915 1
- © 1998, Adaptec, Inc 2
- Electronic Support 4
- Technical and Product Support 4
- Contents 5
- 4 PCI Module Architecture 6
- 7 Register Descriptions 7
- 8 Sample Driver 7
- ▼ ▼ ▼ ▼ 11
- Introduction 15
- Ethernet 16
- Internal Buffer Management 17
- 32/64-bit PCI 17
- Block Diagram 19
- Receive Architecture 21
- Producer and Consumer Indices 22
- Receive DMA Descriptor Queues 22
- Normal Mode 23
- Polling Mode 23
- 32-bit Addressing Mode 24
- 64-bit Addressing Mode 24
- Accepting frames 25
- Start Index 26
- Transmit Architecture 31
- CALTCP bit to zero in the 32
- Transmit Data Structure 34
- Transmit Register Set 35
- PCI Module Architecture 43
- PCI Block Diagram 45
- PCI Master Module 46
- 64-bit PCI Bus Master 47
- Arbitration 48
- Power Management 50
- Retry Function 51
- Response to PCI Commands 51
- Configuration Address Space 53
- Expansion ROM Address Space 54
- Memory Address Space 54
- Illegal Behavior 56
- Frame Processor Architecture 57
- Wake-up Mode 58
- Transmit Checksum Accelerator 58
- GFP Address Space 59
- External Registers 60
- Instruction Formats 62
- AIC-6915 Internal Registers 67
- AIC-6915 Address Space 74
- AIC-6915 PCI Address Map 74
- Terminology 76
- PCI Registers 77
- Byte Address: 04h - 05h 78
- 2:0 r 0 AddressSpaceIndicator 84
- Byte Address: 34h 86
- Byte Address: 3Ch 86
- Byte Address: 3Fh 88
- Byte Address: 40h - 43h 89
- Byte Address: 54h - 57h 95
- Ethernet Registers 99
- Type: R/W 100
- Byte Address: 74h - 77h 100
- Register Descriptions 101
- Transmit Registers 109
- OMPLETION 115
- Byte Address: BCh - BFh 116
- Byte Address: C0h - C3h 117
- Receive Registers 120
- Byte Address: F8h- FBh 130
- PCI Diagnostic Registers 131
- Byte Address: 0104h - 0107h 132
- Byte Address: 011Ch - 011Fh 136
- PCI CardBus Registers 138
- Byte Address: 013Ch - 013Fh 140
- Additional Ethernet Registers 141
- MAC Control Registers 143
- Byte Address: 5004h- 5007h 145
- Byte Address: 5070h - 5073h 152
- Address Filtering Registers 154
- MAC Statistic Registers 156
- Sample Driver 161
- // configuration space 163
- Receive Process 167
- Type 2 Completion Descriptor 168
- Type 3 Completion Descriptor 168
- 32-bit buffer descriptor 168
- 64-bit buffer descriptor 168
- Two Receive Queues 169
- Receive Polling Model 169
- Receive Initialization 169
- Receive Interrupt Handling 175
- Transmit Process 176
- Type 0 descriptor 178
- Type 1 descriptor 178
- Two Transmit Queues 180
- Transmit Initialization 181
- Transmit Handling 185
- AIC-6915 DDK Features 189
- DDK Development Environment 190
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